Associate Professor Peter Sutton's research interests are in Engineering Education, Embedded Computing Systems and Reconfigurable Computing
Associate Professor Peter Sutton has worked, studied and taught in the area of computer systems since completing his undergraduate studies in 1990. His particular research interests are in Engineering Education, Embedded System Design Software, Electronic Design Automation, and Reconfigurable Computing Systems.
Conference Publication: Managing Hands-on Electrical and Computer Engineering Labs during the COVID-19 Pandemic
Wijenayake, Chamith, D'souza, Matthew, Khatamianfar, Arash, Bialkowski, Konstanty, Ros, Montserrat and Sutton, Peter (2021). Managing Hands-on Electrical and Computer Engineering Labs during the COVID-19 Pandemic. IEEE International Conference on Engineering, Technology and Education (IEEE TALE), Wuhan, Peoples Republic of China, 5-8 December 2021. Piscataway, NJ, United States: Institute of Electrical and Electronics Engineers. doi: 10.1109/TALE52509.2021.9678716
Conference Publication: An evidence-based approach to designing a first year Electrical Engineering Course
Bergmann, Neil, O'Shea, Peter, Terrill, Philip and Sutton, Peter (2013). An evidence-based approach to designing a first year Electrical Engineering Course. AAEE 2013: 24th Annual Conference of the Australasian Association for Engineering Education, Gold Coast, QLD, Australia, 8-11 December 2013. Nathan, QLD, Australia: Griffith School of Engineering, Griffith University.
Conference Publication: Using quicksand to improve debugging practice in post-novice level students
Fenwick, Joel and Sutton, Peter (2012). Using quicksand to improve debugging practice in post-novice level students. Fourteenth Australasian Computing Education Conference (ACE2012), Melbourne, Australia, 30 January - 2 February 2012. Sydney, Australia: Australian Computer Society.
TeamAnneal Stage Two: A Web Service for Purposeful Student Team Creation
(2017–2018) UQ Teaching Innovation Grants
TheJourneyMaker: Enhancing curriculum design, program analytics and the student experience
(2015–2016) Technology-Enhanced Learning Grants
(2008–2009) ALTC Priority Projects
Dynamic cache switching: Developing configurable caches for use in softcore processors
(2010) Doctor Philosophy
A New Architecture for Virtual Private Networking with Reconfigurable System-on-Chip Technology
(2007) Doctor Philosophy
CODE COMPRESSION OPTIMISATION FOR VLIW PROCESSORS
(2007) Doctor Philosophy
Engineering Education
I'm interested in many aspects of Engineering and Computer Science Education, particularly technology-enhanced learning. Contact me to discuss ideas!
FPGA implementations of neural networks - A survey of a decade of progress
Zhu, Jihan and Sutton, Peter (2003). FPGA implementations of neural networks - A survey of a decade of progress. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2778, 1062-1066. doi: 10.1007/978-3-540-45234-8_120
An evaluation of active lecturing in a computer networks course
Sutton, P. R. (2003). An evaluation of active lecturing in a computer networks course. World Transactions on Engineering and Technology Education, 2 (2), 185-188.
Managing Hands-on Electrical and Computer Engineering Labs during the COVID-19 Pandemic
Wijenayake, Chamith, D'souza, Matthew, Khatamianfar, Arash, Bialkowski, Konstanty, Ros, Montserrat and Sutton, Peter (2021). Managing Hands-on Electrical and Computer Engineering Labs during the COVID-19 Pandemic. IEEE International Conference on Engineering, Technology and Education (IEEE TALE), Wuhan, Peoples Republic of China, 5-8 December 2021. Piscataway, NJ, United States: Institute of Electrical and Electronics Engineers. doi: 10.1109/TALE52509.2021.9678716
An evidence-based approach to designing a first year Electrical Engineering Course
Bergmann, Neil, O'Shea, Peter, Terrill, Philip and Sutton, Peter (2013). An evidence-based approach to designing a first year Electrical Engineering Course. AAEE 2013: 24th Annual Conference of the Australasian Association for Engineering Education, Gold Coast, QLD, Australia, 8-11 December 2013. Nathan, QLD, Australia: Griffith School of Engineering, Griffith University.
Using quicksand to improve debugging practice in post-novice level students
Fenwick, Joel and Sutton, Peter (2012). Using quicksand to improve debugging practice in post-novice level students. Fourteenth Australasian Computing Education Conference (ACE2012), Melbourne, Australia, 30 January - 2 February 2012. Sydney, Australia: Australian Computer Society.
A unified emulation/simulation environment for reconfigurable system-on-chip development
Crosthwaite, Peter, Williams, John and Sutton, Peter (2011). A unified emulation/simulation environment for reconfigurable system-on-chip development. 2011 International Conference on Field-Programmable Technology, New Dehli, India, 12-14 December 2011. Piscataway, NJ, United States: IEEE. doi: 10.1109/FPT.2011.6132690
Design exploration for FPGA-based multiprocessor architecture: JPEG encoding case study
Wu, Jason, Williams, John, Bergmann, Neil and Sutton, Peter (2009). Design exploration for FPGA-based multiprocessor architecture: JPEG encoding case study. 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, 5-7 April 2009. Piscataway NJ United States: IEEE. doi: 10.1109/FCCM.2009.7
Profile driven data-dependency analysis for improved high level language hardware synthesis
Crosthwaite, Peter, Williams, John and Sutton, Peter (2009). Profile driven data-dependency analysis for improved high level language hardware synthesis. 2009 International Conference on Field-Programmable Technology, Sydney , Australia, 9-11 December 2009. Piscataway NJ USA: IEEE. doi: 10.1109/FPT.2009.5377672
Shield, John, Sutton, Peter and Williams, John (2009). Targeted configurable caches. 8th International Conference on Field-Programmable Technology, Sydney , Australia, 9-11 December 2009. Piscataway NJ, USA: IEEE. doi: 10.1109/FPT.2009.5377674
Analysis of kernel effects on optimisation mismatch in cache reconfiguration
Shield, J., Sutton, P. and Machanick, P. (2007). Analysis of kernel effects on optimisation mismatch in cache reconfiguration. 2007 International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, The Netherlands, 27th - 29th August, 2007. New Jersey, USA: IEEE. doi: 10.1109/FPL.2007.4380732
Dynamic cache switching in reconfigurable embedded systems
Shield, J, Sutton, P. and Machanick, P. (2007). Dynamic cache switching in reconfigurable embedded systems. 2007 International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, The Netherlands, 27th - 29th August, 2007. New Jersey, USA: IEEE. doi: 10.1109/FPL.2007.4380634
Wee, C.M., Sutton, P.R. and Bergmann, N.W. (2007). Operating system integration and performance of a multi stream cipher architecture for reconfigurable system-on-chip. 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), California, USA, 23-25 April, 2007. Piscataway, NJ, USA: IEEE. doi: 10.1109/FCCM.2007.19
Context-enhanced authentication for infrastructureless network environments
Wishart, R. G., Indulska, J., Portmann, M. and Sutton, P. R. (2006). Context-enhanced authentication for infrastructureless network environments. Third International Conference on Ubiquitous Intelligence and Computing, Wuhan, China, 3-6 September, 2006. Berlin: Springer-Verlag Berlin. doi: 10.1007/11833529_94
Multi stream cipher architecture for reconfigurable system-on-chip
Wee, C. M., Sutton, P R, Bergmann, N W and Williams, J A (2006). Multi stream cipher architecture for reconfigurable system-on-chip. 2006 International Conference on Field Programmable Logic and Applications, Madrid, Spain, 28-30 August, 2006. Spain: IEEE Circuits and Systems Society. doi: 10.1109/FPL.2006.311310
VPN acceleration using reconfigurable system-on-chip technology
Wee, C. M., Sutton, P R, Bergmann, N W and Williams, J A (2006). VPN acceleration using reconfigurable system-on-chip technology. 14th Annual IEEE Symposim on Field-Programmable Custom Computing Machines, Napa, California, 24-26 April, 2006. USA: IEEE. doi: 10.1109/FCCM.2006.72
A post-compilation register reassignment technique for improving hamming distance code compression
Ros, Montserrat and Sutton, Peter (2005). A post-compilation register reassignment technique for improving hamming distance code compression. CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, San Francisco, CA, U.S.A., 24-27 September 2005. New York, NY, U.S.A.: ACM Press. doi: 10.1145/1086297.1086311
An FPGA network architecture for accelerating 3DES - CBC
Wee, C. M., Sutton, P. R. and Bergmann, N. W. (2005). An FPGA network architecture for accelerating 3DES - CBC. 15th International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, 24-26 August 2005. Piscataway, N.J.: IEEE. doi: 10.1109/FPL.2005.1515806
A hamming distance based VLIW/EPIC code compression technique
Ros, M. B. and Sutton, P. R. (2004). A hamming distance based VLIW/EPIC code compression technique. The International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2004), Washington, U.S.A., 22-25 September 2004. New York, U.S.A.: ACM Press. doi: 10.1145/1023833.1023853
A hamming distance based VLIW/EPIC code compression technique
Ros, Montserrat and Sutton, Peter (2004). A hamming distance based VLIW/EPIC code compression technique. CASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, Washington, DC United States, 22 - 25 September 2004. ACM.
Architectural tradeoffs in reconfigurable computer for Monte Carlo based simulation of sintering
Postula, A. J., Sutton, P. R., Harrington, D. and Sutton, R. A. (2004). Architectural tradeoffs in reconfigurable computer for Monte Carlo based simulation of sintering. The Work in Progress Session, Rennes, France, 1-4 September, 2004. Austria: SEA Publications.
Code compression based on operand-factorization for VLIW processors
Ros, M. B. and Sutton, P. R. (2004). Code compression based on operand-factorization for VLIW processors. The Data Compression Conference 2004 (DCC 2004), Snowbird, Utah, U.S.A., 23-25 March 2004. Los Alamitos, California, U.S.A.: IEEE Computer Society. doi: 10.1109/DCC.2004.1281535
Memory specification for reconfigurable computing synthesis tools
Xue, J.K. and Sutton, P. R. (2004). Memory specification for reconfigurable computing synthesis tools. The 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, 6-8 December, 2004. Piscataway, NJ: The Institute of Electrical and Electronics Engineers. doi: 10.1109/fpt.2004.1393314
Partial character decoding for improved regular expression matching in FPGAs
Sutton, P. R. (2004). Partial character decoding for improved regular expression matching in FPGAs. The 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, 6-8 December, 2004. Piscataway, NJ: The Institute of Electrical and Electronics Engineers. doi: 10.1109/FPT.2004.1393247
An FPGA Implementation of Kak's Instantaneously-Trained, Fast-Classification Neural Networks
Zhu, J. and Sutton, P. R. (2003). An FPGA Implementation of Kak's Instantaneously-Trained, Fast-Classification Neural Networks. The 2003 IEEE International Conference on Field-Programmable Technology (FPT), Tokyo, Japan, 15-17 December, 2003. Tokyo, Japan: The University of Tokyo. doi: 10.1109/FPT.2003.1275740
Compiler Optimization and Ordering Effects on VLIW Code Compression
Montserrat, Ros and Sutton, Peter (2003). Compiler Optimization and Ordering Effects on VLIW Code Compression. International Conference on Compilers, Architecture and Synthesis for Embedded Systems, San Jose, CA, USA, Oct 30 - Nov 1, 2003. New York: ACM Press. doi: 10.1145/951710.951725
FPGA Implementation of Neural Networks - A Survey of a Decade of Progress
Zhu, Jihan and Sutton, Peter (2003). FPGA Implementation of Neural Networks - A Survey of a Decade of Progress. 13th International Conference on Field-Programmable Logic and Applications (FPL 2003), Lisbon, Portugal, September.
FPGA implementations of neural networks: A survey of a decade of progress
Zhu, J. and Sutton, P. R. (2003). FPGA implementations of neural networks: A survey of a decade of progress. The Thirteenth International Conference on Field-Programmable Logic and Applications, Lisbon, Portugal, 1-3 September, 2003. Berlin: Springer.
Location management in pervasive systems
Indulska, J. and Sutton, P. R. (2003). Location management in pervasive systems. The Australian Information Security Workshop and the Workshop on Wearable, Invisible, Context-Aware, Ambient, Pervasive and Ubiquitous Computing, Adelaide, 4-7 February, 2003. Sydney: Australian Computer Society.
Sutton, P. R., Brereton, M. F., Heyer, C. M. and MacColl, I. D. (2002). Ambient interaction framework: Software infrastructure for the rapid development of pervasive computing environments. Inaugural Asia Pacific Forum on Pervasive Computing, Adelaide, 31 October - 1 November, 2002. Australia: Australian Computer Society.
JPG: A partial bitstream generation tool to support partial reconfiguration in virtex FPGAs
Raghavan, A. and Sutton, P. R. (2002). JPG: A partial bitstream generation tool to support partial reconfiguration in virtex FPGAs. 16th International Parallel and Distributed Processing Symposium, IPDPS 2002, Ft Lauderdale, Florida, 15-19 April, 2002. Los Alamitos, California: IEEE Computer Society. doi: 10.1109/IPDPS.2002.1016552
A flexible multiplacation unit for an FPGA logic block
Rajagopalan, K. and Sutton, P. R. (2001). A flexible multiplacation unit for an FPGA logic block. The IEEE International Symposium on Circuits and Systems, Sydney, 6-9 May, 2001. Piscataway, New Jersey: IEEE. doi: 10.1109/ISCAS.2001.922295
Rajagopalan, K. and Sutton, P. R. (2001). An FPGA architecture with configurable multiplier and carry units for improved arithmetic performance. Ninth International Symposium on Field Programmable Gate Arras, Monterey, California, 11-13 February, 2001. New York: The Association for Computing Machinery.
An innovation design and studio-based CS degree
Docherty, M. J., Sutton, P. R., Brereton, M. F. and Kaplan, S. M. (2001). An innovation design and studio-based CS degree. SIGCSE 2001, Charlotte, North Carolina, 21-25 February 2001. 1515 Broadway, New York, New York 10036: Association for Computing Machinery, Inc. doi: 10.1145/364447.364591
Johnson, D. M., Sutton, P. R. and Harris, N. (2001). Extreme programming requires extremely effective communication: teaching effective communication skills to students in an IT degree. ASCILITE 2001, University of Melbourne, 9-12 December 2001. Melbourne, Victoria: Biomedical Multimedia Unit, University of Melbourne.
Supporting disconnectedness: Transparent information delivery for mobile and invisible computing
Sutton, P. R., Arkins, R. G. and Segall, B. (2001). Supporting disconnectedness: Transparent information delivery for mobile and invisible computing. First IEEE/ACM International Symposium on Cluster Computing and the Grid, Brisbane, 15-18 May, 2001. Los Alamitos, California: IEEE Computer Society. doi: 10.1109/CCGRID.2001.923204
Face-to-face vs CMC: Student communication in a technologically rich learning environment
Johnson, D. M., Sutton, P. R. and Poon, J. (2000). Face-to-face vs CMC: Student communication in a technologically rich learning environment. ASCILITE 2000, Coffs Harbour, 9-14 December 2000. Lismore, NSW: Southern Cross University Press.
The information environments program: A new design based IT degree
Docherty, M., Sutton, P. R., Brereton, M. F., Kaplan, S. M. and Brown, A. (2000). The information environments program: A new design based IT degree. ACE 2000, Melbourne, 4-6 December 2000. New York: ACM. doi: 10.1145/359369.359378
Rapid prototyping and implementation method for systolic array digital signal processors
Bergmann N., Wong H. and Sutton P. (1991). Rapid prototyping and implementation method for systolic array digital signal processors. Tenth Microelectronic Conference, Melbourne, Aust, June 24, 1991-June 25, 1991. Publ by IE Aust.
TeamAnneal Stage Two: A Web Service for Purposeful Student Team Creation
(2017–2018) UQ Teaching Innovation Grants
TheJourneyMaker: Enhancing curriculum design, program analytics and the student experience
(2015–2016) Technology-Enhanced Learning Grants
(2008–2009) ALTC Priority Projects
Concept Inventory Development for computer and Digital Systems
(2007–2009) UQ Teaching & Learning Strategic Grants
Reconfigurable System-on-Chip for Computer Network Appliances
(2004–2007) ARC Linkage Projects
Reconfigurable Computer for Simulation of Sintering At the Atomic Level
(2003) University of Queensland Research Development Grants Scheme
Design of a naturalistic gesture based input applicance for ubiquitous computing environments
(2001) University of Queensland Small Grants Scheme
Efficient Hardware Compilation for Reconfigurable Computing.
(2000) UQ Early Career Researcher
Design process improvement for reconfigurable computing
(1999) UQ New Staff Research Start-Up Fund
Dynamic cache switching: Developing configurable caches for use in softcore processors
(2010) Doctor Philosophy — Principal Advisor
A New Architecture for Virtual Private Networking with Reconfigurable System-on-Chip Technology
(2007) Doctor Philosophy — Principal Advisor
Other advisors:
CODE COMPRESSION OPTIMISATION FOR VLIW PROCESSORS
(2007) Doctor Philosophy — Principal Advisor
PLACE AND ROUTE FOR PARTIAL FPGA RECONFIGURATION
(2004) Master Engineering Sc — Principal Advisor
RTOS Speedup Methods for Hard Real-time Embedded Systems on FPGA
(2013) Doctor Philosophy — Associate Advisor
Design Framework for FPGA-based Multiprocessor
(2012) Doctor Philosophy — Associate Advisor
Other advisors:
Designing context-aware applications for complex environments
(2010) Doctor Philosophy — Associate Advisor
A participatory design approach in the engineering of ubiquitous computing systems
(2009) Doctor Philosophy — Associate Advisor
(2008) Doctor Philosophy — Associate Advisor
Other advisors:
Estimation of Analog Layout Parasitics with Parameterized Polygons
(2008) Doctor Philosophy — Associate Advisor
AN INTERFACE METHODOLOGY FOR RECONFIGURABLE FPGA PERIPHERALS - A FEATURE-BASED APPROACH.
(2006) Master Philosophy — Associate Advisor
HARDWARE ACCELERATION OF SECURITY APPLICATION USING RECONFIGURABLE SYSTEM-ON-CHIP
(2006) Master Philosophy — Associate Advisor
RECONFIGURABLE COMPUTING FOR REAL-TIME APPLICATIONS
(2006) Doctor Philosophy — Associate Advisor
MULTIPLE CONNECTION BASED TCP FOR A WIDE RANGE OF NETWORKS
(2005) Doctor Philosophy — Associate Advisor
Other advisors:
Note for students: The possible research projects listed on this page may not be comprehensive or up to date. Always feel free to contact the staff for more information, and also with your own research ideas.
Engineering Education
I'm interested in many aspects of Engineering and Computer Science Education, particularly technology-enhanced learning. Contact me to discuss ideas!